(1) Field
This embodiment relates to a semiconductor output circuit, an external output signal generation method, and a semiconductor device and, more particularly, to a semiconductor output circuit and an external output signal generation method for generating an external output signal used for transmitting information between chips and a semiconductor device including such a semiconductor output circuit.
(2) Description of the Related Art
The microfabrication technology of large-scale integration (LSI) has raised the integration levels of chips and the number of functional circuits which can be formed on one chip has increased rapidly. However, many of ordinary semiconductor integrated circuit devices do not have a structure in which many functions are performed by one chip, but a structure in which a plurality of chips each having a predetermined function are coupled by bus wirings. Accordingly, each chip includes a (semiconductor) output circuit for outputting a signal used for transmitting information between chips.
FIG. 7 is a circuit diagram showing an example of the structure of a conventional semiconductor output circuit.
FIG. 7 shows an output circuit portion for outputting an external output signal EB from a chip 91 including the semiconductor output circuit to a second chip 93. In this example, a gunning transceiver logic (GTL) output circuit which is one of input-output interfaces is shown.
An internal input signal A electric potential of which changes according to the operation of a functional circuit (not shown) included in the chip 91 is coupled to a gate of a transistor 91b included in an n-channel open drain circuit at an output stage via an inverter 91c. VDD is internal power supply voltage. When the electric potential of the internal input signal A changes from ground to positive power supply voltage (logical value of the internal input signal A changes from L to H), the transistor 91b at the output stage goes into a non-conductive state (off state). As a result, electric potential of an external output signal EB outputted via a pad 91a is raised to terminal voltage VT. When the electric potential of the internal input signal A changes in the reverse direction (logical value of the internal input signal A changes from H to L), the transistor 91b at the output stage goes into a conductive state (on state). As a result, the electric potential of the external output signal EB decreases to output voltage VOL at a low voltage side. At a receiving end, a change of the external output signal EB caused by the turning on and off of the transistor 91b is detected as a slight change in amplitude with respect to reference voltage and the logical value of the external output signal EB is determined. For example, it is fixed that terminal voltage for standard GTL output circuits is 1.2V±5% and that terminal voltage for GTL+ output circuits is 1.5V±10%.
However, as the internal power supply voltage of LSI decreases with an increase in integration level, voltage (Vgs) between the gate and a source of the transistor 91b at the output stage becomes smaller and variation in the DC characteristic becomes larger.
Accordingly, a bias circuit for preventing a drop in saturation output power by controlling Vgs in the case of making a GaAs FET for power amplification operate near a saturation region is proposed (see, for example, Japanese Patent Laid-Open Publication No. Hei9-46141 (FIG. 1)).
In addition, a semiconductor output circuit in which Vgs is controlled by dividing output from a voltage follower and by performing negative feedback is proposed (see, for example, Japanese Patent Laid-Open Publication No. 2002-232243 (FIG. 1)).
By the way, a non-saturation conditional expression of an output buffer is given by|Vgs−Vth|>|Vds|  (1)
If the left side “|Vgs−Vth|” becomes smaller, then an operating point shifts from a non-saturation region to a saturation region. When VDD decreases with an increase in integration level, this is a cause of great variation in the DC characteristic of the transistor 91b at the output stage. Accordingly, variation in the output voltage VOL at the low voltage side of the external output signal EB the level of which depends on the operation of the transistor 91b at the output stage becomes larger.
FIG. 8 is a view showing the output DC characteristics of the output transistor included in the conventional semiconductor output circuit. These DC characteristics are obtained when the voltage of the internal input signal A is low.
When the internal power supply voltage VDD is high, Vgs is large. When the internal power supply voltage VDD becomes lower, Vgs becomes smaller. In FIG. 8, characteristics 95 of the output transistor obtained at the time of Vgs being large before a drop in the internal power supply voltage VDD caused by an increase in integration level and characteristics 96 of the output transistor obtained at the time of Vgs becoming small after the drop in the internal power supply voltage VDD caused by an increase in integration level are shown. A characteristic variation for each Vgs value results from process variation.
Therefore, compared with a variation in VOL (ΔVOL 97) obtained from a load line at the time of Vgs being large, a variation in VOL (ΔVOL 98) obtained at the time of Vgs being small is large. When Vgs is small, the operating point is near the saturation region.
FIG. 9 is a view showing signal waveforms of the conventional semiconductor output circuit. FIG. 9 shows examples of the waveforms of the internal input signal A and the external output signal EB obtained in the case of (A) Vgs=2.5V and (B) Vgs=1.8V.
If (A) Vgs=2.5V, that is to say, if the internal power supply voltage is high and Vgs is large, then a variation in VOL (ΔVOL) of the external output signal EB is 130 mV. If (B) Vgs=1.8V, that is to say, if the internal power supply voltage is low and Vgs drops by 0.7 V, then a variation in VOL (ΔVOL) of the external output signal EB increases to 203 mV.
As has been described, a variation in the DC characteristic of the output transistor and a variation in the output voltage VOL at the low voltage side of the external output signal EB become larger with a decrease in the internal power supply voltage caused by an increase in integration level.